The present invention relates generally to semiconductor memory designs, and, more particularly, to a memory word-line driver design.
The core of a semiconductor memory comprises at least one two-dimensional memory cell array, where information is stored. Traditionally, word-lines select rows, which activate cells, and bit-lines select columns, which access, i.e., read or write, the cells. When a word-line and a bit line are activated, a particular memory cell connected to them is selected.
To activate a word-line, its voltage is normally set to a high voltage, which is equal to a positive supply voltage in a CMOS circuitry. Setting word-line to a low voltage, which is a voltage complimentary to the positive supply voltage, de-activates the word-line. While the low voltage is customarily set to ground, or 0 V, the value for the high voltage can be different for various semiconductor manufacturing technologies. For instance, in a deep-sub-micron technology, a high voltage can be 1.2 V or even lower, while in a sub-micron technology the high voltage can be 2.5 V. But for a given memory chip and a given technology, the high voltage is normally designed to a fixed value, and this is particularly true for a complimentary-metal-oxide-semiconductor (CMOS) memory circuitry.
Since there are multiple memory cells connected to a single word-line, and word-line itself can be very long depending on the memory array size and technology used, so the word-line can be quite a load for its corresponding decoder, then a driver is needed to drive the word-line. The word-line driver couples, on one end, to a word-line decoder output, and on the other end, to a word-line. When a memory chip is in an active mode, i.e., the memory chip is ready for being actively read or written, the word-line driver functions just as a regular driver, following the word-line decoder, and providing a current source to pull up the word-line to a high voltage when the word-line is selected, and pull down the word-line to a low voltage when the word-line is not selected. When the memory chip is in a standby mode, i.e., the memory can not be actively read or written, and the power consumption is maintained at a minimum just to retain the information stored in the memory cell arrays, then the word-line driver clamps the word-line voltage to low. Besides, it is desirable for the word-line driver to have lower stand-by power consumption.
What is needed is an improved word-line driver design with reduced leakage and reduced layout area.